TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-4
Clock Sequencing
Clock
Condition
None
Sequencing
DDRCLK
CORECLK
Must be present 16 μsec before POR transitions high.
CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.
PASSCLK is not used and should be tied to a static state.
None
PASSCLKSEL = 0
PASSCLKSEL = 1
PASSCLK
PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from
reset and programmed.
An SGMII port will be used.
SRIOSGMIICLK must be present 16 μsec before POR transitions high.
SGMII will not be used. SRIO SRIOSGMIICLK must be present 16 μsec before POR transitions high.
will be used as a boot device.
SRIOSGMIICLK
SGMII will not be used. SRIO SRIOSGMIICLK is used as a source to the SRIO SERDES PLL. It must be present before the SRIO is
will be used after boot.
removed from reset and programmed.
SGMII will not be used. SRIO SRIOSGMIICLK is not used and should be tied to a static state.
will not be used.
PCIE will be used as a boot
device.
PCIECLK must be present 16 μsec before POR transitions high.
PCIECLK
PCIE will be used after boot. PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from
reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as a
boot device.
MCMCLK must be present 16usec before POR transitions high.
MCMCLK
HyperLink will be used after MCMCLK is used as a source to the MCM SERDES PLL. It must be present before the HyperLink is
boot. removed from reset and programmed.
HyperLink will not be used. MCMCLK is not used and should be tied to a static state.
End of Table 7-4
7.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
7.2.3 Power Supply Decoupling and Bulk Capacitors
In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are
required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or
bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply
Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation
from Texas Instruments’’ on page 73.
126
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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