TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.2.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the
leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.
This static power consumption is mainly determined by transistor type and process technology. Higher clock rates
also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a
specific usage scenario, clock rates, and I/O activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TMS320C6678 device is a feature that allows the core
voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each
TMS320C6678 device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required
to be implemented whenever the TMS320C6678 device is used. The voltage selection is done using 4 VCNTL pins,
which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices application
report and the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’
on page 73.
Table 7-5
(see Figure 7-3)
SmartReflex 4-Pin VID Interface Switching Characteristics
No.
Parameter
Delay Time - VCNTL[2:0] valid after VCNTL[3] low
Min
Max
300.00
Unit
ns
1
2
3
4
5
td(VCNTL[2:0]-VCNTL[3])
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
0.07 172020C (1)
ms
ns
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] high
300.00
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
VCNTL being valid to CVDD being switched to SmartReflex Voltage (2)
0.07
172020C
10
ms
ms
End of Table 7-5
1
C = 1/SYSCLK1 frequency in ms
2 SmartReflex voltage needs to be set before execution of application code
Figure 7-3
SmartReflex 4-Pin VID Interface Timing
1.1 V
SRV*
* SRV = Smart Reflex Voltage
CVDD
4
5
VCNTL[3]
1
3
VCNTL[2:0]
LSB VID[2:0]
MSB VID[5:3]
2
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 127
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