TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.3.2 Clock Domains
Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-7 shows the TMS320C6678 clock domains.
Table 7-7
Clock Domains
Module(s)
LPSC Number
Notes
0
Shared LPSC for all peripherals other than those listed in this table
Always on
1
SmartReflex
Always on
2
DDR3 EMIF
Always on
3
EMIF16 and SPI
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
4
TSIP
5
Debug Subsystem and Tracers
Per-core TETB and System TETB
Packet Accelerator
Ethernet SGMIIs
6
7
8
9
Security Accelerator
PCIe
10
11
SRIO
12
HyperLink
13
Reserved
14
MSMC RAM
Software control
Always on
15
C66x CorePac0 and Timer 0
C66x CorePac1 and Timer 1
C66x CorePac2 and Timer 2
C66x CorePac3 and Timer 3
C66x CorePac4 and Timer 4
C66x CorePac5 and Timer 5
C66x CorePac6 and Timer 6
C66x CorePac7 and Timer 7
Bootcfg, PSC, and PLL controller
16
Always on
17
Always on
18
Always on
19
Always on
20
Always on
21
Always on
22
Always on
No LPSC
These modules do not use LPSC
End of Table 7-7
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 129
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