TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-2 and defined in Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
Figure 7-2
IO Before Core Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
5
7
RESETFULL
8
GPIO Config
Bits
2a
9
10
RESET
CVDD
3c
2b
6
3a
CVDD1
1
DVDD18
4
DVDD15
3b
REFCLKP&N
DDRCLKP&N
RESETSTAT
124
Peripheral Information and Electrical Specifications
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