TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.2.1.1 Core-Before-IO Power Sequencing
Figure 7-1 shows the power sequencing and reset control of TMS320C6678 for device initialization. POR may be
removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after
the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the
GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.
REFCLK must always be active before POR can be removed. Core-before-IO power sequencing is defined in
Table 7-2.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
Figure 7-1
Core Before IO Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
7
RESETFULL
8
GPIO Config
Bits
4b
9
10
RESET
CVDD
2c
1
6
2a
CVDD1
3
DVDD18
4a
DVDD15
5
REFCLKP&N
DDRCLKP&N
2b
RESETSTAT
122
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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