TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating
off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several
important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
7.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The
global power/sleep controller (GPSC) is used to control the power gating of various power domains.
Table 7-6 shows the TMS320C6678 power domains.
Table 7-6
Power Domains
Domain
Block(s)
Note
Power Connection
Always on
0
Most peripheral logic
Per-core TETB and System TETB
Packet Coprocessor
PCIe
Cannot be disabled
RAMs can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Reserved
1
Software control
Software control
Software control
Software control
Software control
Reserved
2
3
4
SRIO
5
HyperLink
6
Reserved
7
MSMC RAM
MSMC RAM can be powered down
L2 RAMs can sleep
Software control
8
C66x CorePac0, L1/L2 RAMs
C66x CorePac1, L1/L2 RAMs
C66x CorePac2, L1/L2 RAMs
C66x CorePac3, L1/L2 RAMs
C66x CorePac4, L1/L2 RAMs
C66x CorePac5, L1/L2 RAMs
C66x CorePac6, L1/L2 RAMs
C66x CorePac7, L1/L2 RAMs
9
L2 RAMs can sleep
10
11
12
13
14
15
L2 RAMs can sleep
L2 RAMs can sleep
Software control via C66x core. For details, see the
C66x CorePac Reference Guide.
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
End of Table 7-6
128
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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