TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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Table 2-14
C66x DSP System PLL Configuration Part 2 (1) (Part 2 of 2)
1250 MHz Device
PLLM DSP ƒ
1500 MHz Device
PLLM DSP ƒ
47
121
PASS PLL = 350 MHz (2)
PLLD PLLM
DSP ƒ (3)
24 167 1050
11 204 1049.6
BOOTMODE
[12:10]
Input Clock
Freq (MHz)
PLLD
PLLD
0b110
312.50
122.88
0
7
1250
4
1500
0b111
2
60
1249.28
4
1499.14
End of Table 2-14
1 The PLL boot configuration of initial silicon 1.0 may only support 800MHz, 1000MHz and 1200MHz frequencies by default.
2 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
3 ƒ represents frequency in MHz.
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
Copyright 2012 Texas Instruments Incorporated
Device Overview 35
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