TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
6
5
4
3
Reserved
Data Rate
Ref Clock
Reserved
Table 2-12
HyperLink Boot Device Configuration Field Descriptions
Bit
9
Field
Description
Reserved
Reserved
8-7
Data Rate
Ref Clocks
Reserved
HyperLink data rate configuration
0 = 1.25 GBaud
1 = 3.125 GBaud
2 = 6.25 GBaud
3 = Reserved
6-5
4-3
HyperLink reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
Reserved
End of Table 2-12
Copyright 2012 Texas Instruments Incorporated
Device Overview 33
TI [ TEXAS INSTRUMENTS ]
