TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Changed EMAC to Gigabit Ethernet Switch (Page 69)
Changed EMAC to Network Coprocessor Packet DMA (Page 91)
Changed Ethernet MAC Subsystem to Gigabit Ethernet Switch Subsystem in Features (Page 13)
Changed PA_SS into Network Coprocessor Packet DMA in Device Master Settings table (Page 178)
Changed PA_SS into PASS in the Clock Sequencing table (Page 119)
Changed PASS into Network Coprocessor (PASS) (Page 133)
Changed PS_SS_CLK PLL to PASS_CLK PLL in Terminal Functions table (Page 41)
Changed Packet Accelerator into Network Coprocessor and corrected the memory address in the memory map summary table (Page 21)
Changed Packet Accelerator into Network Coprocessor in the Device Configuration Pins table. (Page 70)
Changed Packet Subsystem to Network Coprocessor (PASS PLL) in Terminal Functions table (Page 41)
Changed packet accelerator into network coprocessor in Security Accelerator section (Page 210)
Changed packet accelerator subsystem into Network Coprocessor (Page 148)
Deleted section 5.5 "C66x CorePac Resets" to avoid confusion and the reset details are covered in "Reset Controller" section (Page 101)
Removed EMAC in Characteristics of the device Processor table (Page 17)
Added BGA Package row into Characteristics of Processor table (Page 17)
Corrected End and Bytes of DDR3 EMIF Configuration section in Memory Map Summary table (Page 21)
Corrected BAR number from BAR1/2 to BAR2/3 and BAR3/4 to BAR4/5 in PCIe Window Sizes table (Page 31)
Deleted EDMA3 Peripheral Register Description section, which is covered in EDMA user’s guide (Page 150)
Added SERDES PLL Status and Config registers (Page 71)
Added "to DDR3 memory space" to the first step of workaround (Page 191)
Added "with TCCMOD=0" after "e.g. EDMA3 transfer controllers" (Page 191)
Added CPTS_RFTCLK_SEL register in GbE Switch Subsystem section (Page 211)
Changed "DSP/2" to "CPU/2" and "DSP/3" to "CPU/3" (Page 91)
Changed the word "can" to "must" in the sentence "for most applications increment mode can be used" to specify it is a hard rule.
(Page 151)
Changed "sleep boot" to "No boot" in Sub-Mode field of No boot/EMIF16 Configuration Bit Field Descriptions table (Page 29)
Changed Section 2.5.2.1title from "Sleep/EMIF16" to "No Boot/EMIF16" (Page 29)
Corrections Applied to I2C Passive Mode Device Configuration Bit Fields (Page 32)
Corrections Applied to I2C Passive Mode Device Configuration Field Descriptions (Page 32)
Modified description of value 0 to EMIF16/No Boot in Boot Device Values table (Page 28)
Corrected SRIO configuration memory map from 0x02900000~0x02907FFF to 0x02900000~0x02920FFF (Page 21)
Added thermal values into the Thermal Resistance Characteristics table. (Page 223)
Added DDR3PLLCTL1 register and field description table (Page 145)
Added PASSPLLCTL1 register and field descriptions (Page 149)
Added more description to pin PTV15 in the Terminal Functions table (Page 42)
Added Master ID Settings table. (Page 179)
Added the table of Power Supply to Peripheral I/O Mapping (Page 112)
Changed PROGn_MPEAR register table format and reset value format (Page 187)
Changed PROGn_MPSAR registers table format and reset value format (Page 186)
Modified reset values of PROGn_MPPA registers (Page 190)
Modified the figure of SmartReflex 4-Pin VID Interface Timing (Page 120)
Modified the table of SmartReflex 4-Pin VID Interface Switching Characteristics (Page 120)
Added PROG4 registers set into MPU1 Registers table (Page 182)
Changed number of programmable ranges supported from 4 to 5 for MPU1 (Page 178)
Modified Table 2-13 to include 1000 MHz and 1250 MHz columns. (Page 34)
Modified Table 2-13 to include 1000 MHz and 1250 MHz columns. (Page 34)
Modified reset values in MPU Configuration Register table (Page 185)
Added BWADJ[11:8] to MAINPLLCTL1 register table and description. (Page 142)
Changed PROG3_MPEA to PROG3_MPEAR in MPU1 Registers table (Page 182)
Changed Privilege ID from the second column to the first column (Page 178)
Changed Programmable range enumeration from 1-N based to 0-N based in MPU Register Map. (Page 181)
Changed SRIO_CPPI and SRIO_M rows to the single row (Page 178)
Changed the master from Reserved to HyperLink with Privilege ID 13 and 14 (Page 178)
Modified BWADJ descriptions in MAINPLLCTL0 and MAINPLLCTL1 registers (Page 141)
Copyright 2012 Texas Instruments Incorporated
Revision History 221
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