TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.27.3.2 JTAG Electrical Data/Timing
Table 7-86
JTAG Test Port Timing Requirements
(see Figure 7-61)
No.
Min
34
Max Unit
1
tc(TCK)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
1a
1b
3
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
input setup time, TDI valid to TCK high
input setup time, TMS valid to TCK high
input hold time, TDI valid from TCK high
input hold time, TMS valid from TCK high
13.6
13.6
3.4
3.4
17
tw(TCKL)
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
3
4
4
17
End of Table 7-86
Table 7-87
(see Figure 7-61)
JTAG Test Port Switching Characteristics (1)
Parameter
No.
Min
Max Unit
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
13.6
ns
End of Table 7-87
1 Over recommended operating conditions.
Figure 7-61
JTAG Test-Port Timing
1
1a
1b
TCK
TDO
2
4
3
TDI / TMS
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 219
TI [ TEXAS INSTRUMENTS ]
