TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.27.2.1 Trace Electrical Data/Timing
(1)
Table 7-85
Trace Switching Characteristics
(see Figure 7-60)
No.
Parameter
Min Max Unit
1
1
2
2
3
tw(DPnH)
Pulse duration, DPn/EMUn high
2.4
1.5
2.4
1.5
-1
ns
ns
ns
ns
ns
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
tw(DPnL) Pulse duration, DPn/EMUn low
tw(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh
tsko(DPn)
tskp(DPn)
Output skew time, time delay difference between DPn/EMUn pins configured as trace
1
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays.
600 ps
V/ns
tσλδπ_ο(DPn) Output slew rate DPn/EMUn
3.3
End of Table 7-85
1 Over recommended operating conditions.
Figure 7-60
Trace Timing
A
TPLH
TPHL
1
2
B
C
3
7.27.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.27.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6672 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
218
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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