TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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A Revision History
Revision C
Added one note stating that both SGMII ports can be used for boot (Page 30)
Updated the DDR3 MMR descriptions and deleted the unrelated PCIe MMR descriptions for soft reset. (Page 128)
Corrected physical 36-bit addresses of DDR3 EMIF configuration/data (Page 27)
Added TeraNet connection figures and added bridge numbers to the connection tables. (Page 92)
Restricted Output Divide of SECCTL register to max value of divide by 2 (Page 136)
Updated DEVSPEED register for both silicon rev1.0 and 2.0 (Page 89)
Removed RESETFULLz parameter from 4b timing description (Page 116)
Added supported data rates for HyperLink (Page 200)
Updated PLL lock time max value (Page 134)
Changed chip level interrupt controller name from INTC to CIC (Page 156)
Changed TPCC to EDMA3CC and TPTC to EDMA3TC (Page 150)
Added PLLRST bit to DDR3PLLCTL1 register (Page 146)
Added PLLRST bit to PASSPLLCTL1 register (Page 149)
Deleted INTC0 register map address offset 0x4 and 0x8 which are Reserved (Page 170)
Corrected the SGMII SerDes clock to PASS clock in PASS PLL configuration description (Page 34)
Corrected PASS PLL clock from SRIOSGMIICLK to PASSCLK in the boot device values table for Ethernet. (Page 28)
Corrected the SPI and DDR3/Hyperbridge Config end addressed (Page 27)
Added the DDR3 PLL Initialization Sequence (Page 146)
Added the Main PLL and PLL Controller Initialization Sequence (Page 142)
Added the PASS PLL Initialization Sequence (Page 149)
Added HyperLink interrupt event section (Page 200)
Added events #144-159 to INTC2 event input table (Page 164)
Added DEVSPEED Register section. (Page 89)
Added more description to Boot Sequence section (Page 27)
Corrected a typo, changed DDRCLKN to DDRCLKP (Page 147)
Revision B
Removed section 7.1 Parameter Information (Page 113)
Corrected PASS PLL clock source description from Main PLL mux to CORECLK clock reference sources (Page 148)
Corrected MACID2 address from 0x02600114 to 0x02620114 (Page 211)
Added EMIF16 Electrical Data/Timing section (Page 208)
Added TSIP Electrical Data/Timing section (Page 206)
Updated SPI Timing section (Page 197)
Changed Data Rate 3 to Reserved from 12.5GBs in HyperLink configuration field table (Page 33)
Corrected the Device ID field to be bits 5 to 3 in Ethernet Configuration Field figure and table (Page 30)
Corrected the field bits of No Boot/EMIF16 configuration field figure and table (Page 29)
Revision A
Added note to RSISO register that both SRIOISO and SRISO will be set by boot ROM code during boot (Page 141)
Modified PCIe peripherals introduction in Features section (Page 13)
Removed AIF2ISO from Reset Isolation Register (Page 141)
Added information of on-chip divider (=3) for PA in the PLL Boot Configuration Settings section (Page 34)
Changed "no support for MSI" to "support for legacy INTx" for PCIe in legacy EP mode description in Device Status Register Field Descrip-
tions table (Page 75)
Changed "no support for MSI" to "support for legacy INTx" for PCIe legacy end point description in Device Configuration Pins table
(Page 70)
Added "The packet accelerator is coupled with network coprocessor" in the Packet Accelerator section (Page 210)
Added Network Coprocessor document link (Page 69)
Changed 2 to OUTPUT_DIVIDE in the clock formula in PLL Boot Configuration Settings section (Page 34)
Changed EMAC to GbE switch subsystem (Page 211)
Changed EMAC to Gigabit Ethernet (GbE) Switch Subsystem (Page 213)
220
Revision History
Copyright 2012 Texas Instruments Incorporated
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