TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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7.14.2 HyperLink Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of HyperLink peripheral.
Table 7-69
HyperLink Peripheral Timing Requirements
See Figure 7-40,Figure 7-41,Figure 7-42
No.
Min
Max
Unit
FL Interface
Clock period - MCMTXFLCLK (C1)
1
2
3
6
7
6
7
tc(MCMTXFLCLK)
6.4
ns
tw(MCMTXFLCLKH)
High pulse width - MCMTXFLCLK
0.4*C1 0.6*C1 ns
0.4*C1 0.6*C1 ns
tw(MCMTXFLCLKL)
Low pulse width - MCMTXFLCLK
tsu(MCMTXFLDAT-MCMTXFLCLKH)
th(MCMTXFLCLKH-MCMTXFLDAT)
tsu(MCMTXFLDAT-MCMTXFLCLKL)
th(MCMTXFLCLKL-MCMTXFLDAT)
Setup time - MCMTXFLDAT valid before MCMTXFLCLK high
Hold time - MCMTXFLDAT valid after MCMTXFLCLK high
Setup time - MCMTXFLDAT valid before MCMTXFLCLK low
Hold time - MCMTXFLDAT valid after MCMTXFLCLK low
PM Interface
1
1
1
1
ns
ns
ns
ns
1
2
3
6
7
6
7
tc(MCMRXPMCLK)
tw(MCMRXPMCLK)
tw(MCMRXPMCLK)
Clock period - MCMRXPMCLK (C3)
6.4
ns
High pulse width - MCMRXPMCLK
0.4*C3 0.6*C3 ns
0.4*C3 0.6*C3 ns
Low pulse width - MCMRXPMCLK
tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup time - MCMRXPMDAT valid before MCMRXPMCLK high
th(MCMRXPMCLKH-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK high
tsu(MCMRXPMDAT-MCMRXPMCLKL) Setup time - MCMRXPMDAT valid before MCMRXPMCLK low
th(MCMRXPMCLKL-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK low
1
1
1
1
ns
ns
ns
ns
End of Table 7-69
Table 7-70
HyperLink Peripheral Switching Characteristics
See Figure 7-40,Figure 7-41,Figure 7-42
No.
Parameter
FL Interface
Min
Max
Unit
1
2
3
4
5
4
5
tc(MCMRXFLCLK)
Clock period - MCMRXFLCLK (C2)
6.4
ns
tw(MCMRXFLCLKH)
High pulse width - MCMRXFLCLK
0.4*C2 0.6*C2 ns
0.4*C2 0.6*C2 ns
tw(MCMRXFLCLKL)
Low pulse width - MCMRXFLCLK
tosu(MCMRXFLDAT-MCMRXFLCLKH)
toh(MCMRXFLCLKH-MCMRXFLDAT)
tosu(MCMRXFLDAT-MCMRXFLCLKL)
toh(MCMRXFLCLKL-MCMRXFLDAT)
Setup time - MCMRXFLDAT valid before MCMRXFLCLK high
Hold time - MCMRXFLDAT valid after MCMRXFLCLK high
Setup time - MCMRXFLDAT valid before MCMRXFLCLK low
Hold time - MCMRXFLDAT valid after MCMRXFLCLK low
PM Interface
0.25*C2-0.4
ns
ns
ns
ns
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
1
2
3
4
5
4
5
tc(MCMTXPMCLK)
tw(MCMTXPMCLK)
tw(MCMTXPMCLK)
Clock period - MCMTXPMCLK (C4)
6.4
ns
High pulse width - MCMTXPMCLK
0.4*C4 0.6*C4 ns
0.4*C4 0.6*C4 ns
Low pulse width - MCMTXPMCLK
tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup time - MCMTXPMDAT valid before MCMTXPMCLK high
toh(MCMTXPMCLKH-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK high
tosu(MCMTXPMDAT-MCMTXPMCLKL) Setup time - MCMTXPMDAT valid before MCMTXPMCLK low
toh(MCMTXPMCLKL-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK low
0.25*C4-0.4
ns
ns
ns
ns
0.25*C4-0.4
0.25*C4-0.4
0.25*C4-0.4
End of Table 7-70
202
Peripheral Information and Electrical Specifications
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