TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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7.10.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also only writeable by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-33
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-59
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
END_ADDR
Reserved
End address for range n.
Reserved and these bits always read as 3FFh.
End of Table 7-59
Table 7-60
Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
Register
MPU0
MPU1
0x3401_FFFF
0x3405_FFFF
0x3406_7FFF
0x340B_7FFF
0x340B_FFFF
N/A
MPU2
MPU3
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
End of Table 7-60
0x01D8_03FF
0x01F7_FFFF
0x0209_FFFF
0x01EB_FFFF
0x021E_0FFF
0x021F_7FFF
0x022F_03FF
0x0231_03FF
0x0232_03FF
0x0233_03FF
0x0235_0FFF
0x024B_3FFF
0x0252_03FF
0x0254_03FF
0x0260_FFFF
0x0262_07FF
0x02A1_FFFF
0x02A3_FFFF
0x02A5_FFFF
0x02A6_7FFF
0x02A6_8FFF
0x02A6_9FFF
0x02A6_AFFF
0x02A6_BFFF
0x02A6_DFFF
0x02A6_FFFF
0x02A8_FFFF
0x02A9_FFFF
0x02AA_7FFF
0x02AA_FFFF
0x02AB_7FFF
0x02AB_FFFF
0x0264_07FF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 187
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