TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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Table 7-41
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 2 of 3)
Input Event # on CIC
System Interrupt
TETBACQINT
TETBHFULLINT0
TETBFULLINT0
TETBACQINT0
TETBHFULLINT1
TETBFULLINT1
TETBACQINT1
Reserved
Description
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
System TETB acquisition has been completed
TETB0 is half full
TETB0 is full
TETB0 acquisition has been completed
TETB1 is half full
TETB1 is full
TETB1 acquisition has been completed
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
Reserved
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Reserved
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_SS_CFG_INTD
TRACER_QM_SS_DMA_INTD
TRACER_SEM_INTD
VUSR_INT_O
Reserved
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 SCR
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave port
Tracer sliding time window interrupt for semaphore
HyperLink interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR3_ERR
DDR3 EMIF Error interrupt
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Peripheral Information and Electrical Specifications 169
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