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TMS320C6672ACYP25 参数 Datasheet PDF下载

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型号: TMS320C6672ACYP25
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内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 228 页 / 2410 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320C6672  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS708C—February 2012  
www.ti.com  
7.5.2.6 Reset Type Status Register (RSTYPE)  
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur  
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in  
Figure 7-13 and described in Table 7-20.  
Figure 7-13  
Reset Type Status Register (RSTYPE)  
31  
29  
28  
EMU-RST  
R-0  
27  
12  
11  
8
7
3
2
1
0
Reserved  
R-0  
Reserved  
R-0  
WDRST[N]  
R-0  
Reserved  
R-0  
PLLCTRLRST  
R-0  
RESET  
R-0  
POR  
R-0  
Legend: R = Read only; -n = value after reset  
Table 7-20  
Reset Type Status Register (RSTYPE) Field Descriptions  
Bit  
Field  
Description  
31-29 Reserved  
Reserved. Read only. Always reads as 0. Writes have no effect.  
28  
EMU-RST  
Reset initiated by emulation.  
0 = Not the last reset to occur.  
1 = The last reset to occur.  
27-12 Reserved  
Reserved. Read only. Always reads as 0. Writes have no effect.  
11  
10  
9
WDRST3  
WDRST2  
WDRST1  
WDRST0  
Reserved  
PLLCTLRST  
Reset initiated by watchdog timer[N].  
0 = Not the last reset to occur.  
1 = The last reset to occur.  
8
7-3  
2
Reserved. Read only. Always reads as 0. Writes have no effect.  
Reset initiated by PLLCTL.  
0 = Not the last reset to occur.  
1 = The last reset to occur.  
1
0
RESET  
POR  
RESET reset.  
0 = RESET was not the last reset to occur.  
1 = RESET was the last reset to occur.  
Power-on reset.  
0 = Power-on reset was not the last reset to occur.  
1 = Power-on reset was the last reset to occur.  
End of Table 7-20  
7.5.2.7 Reset Control Register (RSTCTRL)  
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value  
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG  
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register  
(RSTCTRL) is shown in Figure 7-14 and described in Table 7-21.  
Figure 7-14  
Reset Control Register (RSTCTRL)  
31  
17  
16  
15  
0
Reserved  
R-0x0000  
SWRST  
R/W-0x (1)  
KEY  
R/W-0x0003  
Legend: R = Read only; -n = value after reset;  
1 Writes are conditional based on valid key.  
Copyright 2012 Texas Instruments Incorporated  
Peripheral Information and Electrical Specifications 139  
 
 
 
 
 
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