TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.5 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL
controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 69.
The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-7 shows a block diagram of the main PLL and the PLL
controller.
Figure 7-7
Main PLL and PLL Controller
PLL
PLLD xPLLM /2
CORECLK(N|P)
0
1
PLLOUT
OUTPUT
DIVIDE
BYPASS
PLL Controller
/1
1
0
SYSCLK1
C66x
CorePac
PLLDIV1
/x
/2
/3
/y
1
0
0
PLLDIV2
PLLDIV3
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
PLLDIV9
PLLDIV10
PLLDIV11
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
SYSCLK8
SYSCLK9
SYSCLK10
SYSCLK11
PLLEN
PLLENSRC
/64
/6
To Switch Fabric,
Peripherals,
Accelerators
/z
/12
/3
/6
132
Peripheral Information and Electrical Specifications
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