TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-8
PSC Register Memory Map (Part 3 of 3)
Offset
Register
MDCTL19
MDCTL20
MDCTL21
MDCTL22
Reserved
Description
0xA4C
Reserved
Reserved
Reserved
Reserved
Reserved
0xA50
0xA54
0xA58
0xA5C - 0xFFC
End of Table 7-8
7.4 Reset Controller
The reset controller detects the different type of resets supported on the TMS320C6672 device and manages the
distribution of those resets throughout the device.
The device has several types of resets:
•
•
•
•
Power-on reset
Hard reset
Soft reset
CPU local reset
Table 7-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /
Timing’’ on page 130
Table 7-9
Reset Type
Reset Types
Initiator
Effect on Device When Reset Occurs
RESETSTAT Pin Status
POR (Power On Reset) POR pin active low
RESETFULL pin active low
Total reset of the chip. Everything on the device is reset to its default
state in response to this. Activates the POR signal on chip, which is used
to reset test/emu logic. Boot configurations are latched. ROM boot
process is initiated.
Toggles RESETSTAT pin
Hard Reset
RESET pin active low
Resets everything except for test/emu logic and reset isolation
modules. Emulator and reset Isolation modules stay alive during this
reset. This reset is also different from POR in that the PLLCTL assumes
power and clocks are stable when device reset is asserted. Boot
configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
Toggles RESETSTAT pin
Emulation
PLLCTL register (RSCTRL)
Watchdog timers
Soft Reset
RESET pin active low
PLLCTL register (RSCTRL)
Watchdog timers
Software can program these initiators to be hard or soft. Hard reset is
the default, but can be programmed to be soft reset. Soft reset will
behave like hard reset except that PCIe MMRs,EMIF16 MMRs, DDR3
EMIF MMRs, and external memory contents are retained. Boot
configurations are not latched. ROM boot process is initiated.
C66x CorePac
local reset
Software (through
LPSC MMR)
MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog Does not toggle
timers (in the event of a timeout) to reset C66x CorePac. Can also be
initiated by LRESET device pin. C66x CorePac memory system and slave
DMA port are still alive when C66x CorePac is in local reset. Provides a
local reset of the C66x CorePac, without destroying clock alignment or
memory contents. Does not initiate ROM boot process.
RESETSTAT pin
Watchdog timers
LRESET pin
End of Table 7-9
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 125
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