TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
7.3.2 Clock Domains
Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-7 shows the TMS320C6672 clock domains.
Table 7-7
Clock Domains
Module(s)
LPSC Number
Notes
0
Shared LPSC for all peripherals other than those listed in this table
Always on
1
SmartReflex
Always on
2
DDR3 EMIF
Always on
3
EMIF16 and SPI
TSIP
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
4
5
Debug Subsystem and Tracers
Per-core TETB and System TETB
Packet Accelerator
Ethernet SGMIIs
Security Accelerator
PCIe
6
7
8
9
10
11
SRIO
12
HyperLink
13
Reserved
14
MSMC RAM
Software control
Always on
15
C66x CorePac 0 and Timer 0
C66x CorePac 1 and Timer 1
Reserved
16
Always on
17
Reserved
18
Reserved
Reserved
19
Reserved
Reserved
20
Reserved
Reserved
21
Reserved
Reserved
22
Reserved
Reserved
No LPSC
Bootcfg, PSC, and PLL controller
These modules do not use LPSC
End of Table 7-7
122
Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
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