ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only]
(CONTINUED)
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
PCBE0
W3
I/O/Z
O
For the C6414T device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
For the C6414T device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
XSP_CS
AD1
IPD
CLKX2/
XSP_CLK
AC2
AB3
AA2
I/O/Z
I
IPD
IPU
IPU
McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).
§
McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
§
DR2/XSP_DI
McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
§
DX2/XSP_DO
O/Z
§
GP15/PRST
G3
F2
G4
J3
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
§
GP13/PINTA
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
§
§
GP12/PGNT
GP11/PREQ
I/O/Z
F1
L2
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
§
GP10/PCBE3
§
GP9/PIDSEL
M3
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
ꢁ
||
EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3
ACE2
ACE1
ACE0
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
APDT
L26
K23
K24
K25
T23
T24
R25
R26
M25
M26
L23
L24
M22
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
EMIFA byte-enable control
•
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFA peripheral data transfer, allows direct transfer between external peripherals
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
§
||
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45
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