ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
I
I
Device reset
Nonmaskable interrupt, edge-driven (rising edge)
NMI
B4
IPD
IPU
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it
is recommended that the NMI pin be grounded versus relying on the IPD.
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
AF4
AD5
AE5
AF5
G3
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
default after reset setting is GPIO enabled as input-only.
•
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
I/O/Z
§
GP15/PRST
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
F2
§
GP13/PINTA
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
§
GP12/PGNT
GP11/PREQ
J3
§
F1
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only.
§
GP10/PCBE3
L2
I/O/Z
§
GP9/PIDSEL
M3
AC6
GP3
IPD
IPD
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)
[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)
signal (output only).
GP0
AF6
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro-
grammed as a GPIO 8 pin (I/O/Z).
§¶
CLKS2/GP8
AE4
AD6
AE6
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
§¶
§¶
CLKOUT6/GP2
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
CLKOUT4/GP1
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only]
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI_EN
AA4
I
IPD
PCI peripherals. This pin works in conjunction with the MCBSP2_EN pin to enable/disable
other peripherals (for more details, see the Device Configurations section of this data sheet).
§
HINT/PFRAME
R4
R1
I/O/Z
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
HCNTL1/
Host control − selects between control, address, or data registers (I) [default] or PCI device
select (I/O/Z).
§
PDEVSEL
HCNTL0/
PSTOP
Host control − selects between control, address, or data registers (I) [default] or PCI stop
(I/O/Z)
T4
I/O/Z
§
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
§
HHWIL/PTRDY
R3
P1
I/O/Z
I/O/Z
§
HR/W/PCBE2
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
§
¶
For the C6414T device, only these pins are multiplexed pins.
43
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TI [ TEXAS INSTRUMENTS ]
