ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
ꢁ
||
EMIFA (64-BIT) − BUS ARBITRATION
AHOLDA
AHOLD
N22
V23
P22
O
I
IPU
IPU
IPU
EMIFA hold-request-acknowledge to the host
EMIFA hold request from the host
EMIFA bus request output
ABUSREQ
O
ꢁ
||
EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKIN
H25
I
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT2
AECLKOUT1
J23
J26
O/Z
O/Z
IPD
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
AARE/
ASDCAS/
ASADS/ASRE
•
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
J25
J24
O/Z
O/Z
IPU
IPU
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
AAWE/
ASDWE/
ASWE
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
K26
L25
O/Z
O/Z
IPU
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
ASDCKE
•
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
AARDY
R22
L22
O/Z
I
IPU
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
Asynchronous memory ready input
ꢁ
||
EMIFA (64-BIT) − ADDRESS
AEA22
AEA21
AEA20
AEA19
AEA18
AEA17
AEA16
AEA15
AEA14
AEA13
AEA12
AEA11
T22
V24
V25
V26
U23
U24
U25
U26
T25
T26
R23
R24
O/Z
IPD
EMIFA external address (doubleword address)
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ
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46
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