ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
ꢁ
||
EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
BCE3
A13
C12
B12
A12
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
EMIFB memory space enables
BCE2
BCE1
BCE0
•
•
Enabled by bits 26 through 31 of the word address
Only one pin is asserted during any external data access
EMIFB byte-enable control
BBE1
D13
O/Z
IPU
•
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BBE0
BPDT
C13
E12
O/Z
O/Z
IPU
IPU
EMIFB peripheral data transfer, allows direct transfer between external peripherals
ꢁ
||
EMIFB (16-BIT) − BUS ARBITRATION
BHOLDA
BHOLD
E13
B19
E14
O
I
IPU
IPU
IPU
EMIFB hold-request-acknowledge to the host
EMIFB hold request from the host
EMIFB bus request output
BBUSREQ
O
ꢁ
||
EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BECLKIN
A11
I
IPD
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided by 1, 2, or 4.
BECLKOUT2
BECLKOUT1
D11
D12
O/Z
O/Z
IPD
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
BARE/
BSDCAS/
BSADS/BSRE
•
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between BSADS and BSRE:
A10
O/Z
IPU
If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.
If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.
BAOE/
BSDRAS/
BSOE
EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
B11
C11
O/Z
O/Z
IPU
IPU
BAWE/BSDWE/
BSWE
EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
BSOE3
BARDY
E15
E11
O/Z
I
IPU
IPU
EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
EMIFB asynchronous memory ready input
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ
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49
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TI [ TEXAS INSTRUMENTS ]
