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TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ  
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ  
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
DEVICE CONFIGURATIONS (CONTINUED)  
Table 29. C6414T, C6415T, and C6416T Device Multiplexed Pins  
MULTIPLEXED PINS  
NAME  
DEFAULT FUNCTION  
DEFAULT SETTING  
DESCRIPTION  
NO.  
These pins are software-configurable.  
To use these pins as GPIO pins, the  
GPxEN bits in the GPIO Enable  
Register and the GPxDIR bits in the  
GPIO Direction Register must be  
properly configured.  
CLKOUT4/GP1  
CLKOUT6/GP2  
AE6  
CLKOUT4  
GP1EN = 0 (disabled)  
AD6  
AE4  
CLKOUT6  
CLKS2  
GP2EN = 0 (disabled)  
GP8EN = 0 (disabled)  
GPxEN = 1: GPx pin enabled  
GPxDIR = 0: GPx pin is an input  
GPxDIR = 1: GPx pin is an output  
CLKS2/GP8  
GP9/PIDSEL  
GP10/PCBE3  
GP11/PREQ  
GP12/PGNT  
GP13/PINTA  
GP14/PCLK  
GP15/PRST  
M3  
L2  
To use GP[15:9] as GPIO pins, the PCI  
needs to be disabled (PCI_EN = 0), the  
GPxEN bits in the GPIO Enable  
Register and the GPxDIR bits in the  
GPIO Direction Register must be  
properly configured.  
F1  
GPxEN = 0 (disabled)  
PCI_EN = 0 (disabled)  
J3  
None  
G4  
GPxEN = 1: GPx pin enabled  
GPxDIR = 0: GPx pin is an input  
GPxDIR = 1: GPx pin is an output  
F2  
G3  
DX1/UXADDR4  
FSX1/UXADDR3  
FSR1/UXADDR2  
DR1/UXADDR1  
CLKX1/URADDR4  
CLKS1/URADDR3  
CLKR1/URADDR2  
CLKX2/XSP_CLK  
DR2/XSP_DI  
AB11  
AB13  
AC9  
AF11  
AB12  
AC8  
AC10  
AC2  
AB3  
DX1  
FSX1  
By default, McBSP1 is enabled upon  
reset (UTOPIA is disabled).  
To enable the UTOPIA peripheral, an  
external pullup resistor (1 k) must be  
provided on the BEA11 pin (setting  
UTOPIA_EN = 1 at reset).  
FSR1  
UTOPIA_EN (BEA11) = 0  
(disabled)  
DR1  
CLKX1  
CLKS1  
CLKR1  
CLKX2  
DR2  
DX2/XSP_DO  
AA2  
DX2  
HD[31:0]/AD[31:0]  
HAS/PPAR  
HD[31:0]  
HAS  
T3  
R1  
T4  
T1  
T2  
P1  
R3  
R4  
R2  
P4  
By default, HPI is enabled upon reset  
(PCI is disabled).  
HCNTL1/PDEVSEL  
HCNTL0/PSTOP  
HDS1/PSERR  
HCNTL1  
HCNTL0  
HDS1  
To enable the PCI peripheral an external  
pullup resistor (1 k) must be provided  
on the PCI_EN pin (setting PCI_EN = 1  
at reset).  
PCI_EN = 0 (disabled)  
HDS2/PCBE1  
HDS2  
HR/W/PCBE2  
HR/W  
HHWIL/PTRDY  
HINT/PFRAME  
HCS/PPERR  
HHWIL (HPI16 only)  
HINT  
HCS  
HRDY/PIRDY  
HRDY  
§
For the C6415T and C6416T devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is  
disabled [UTOPIA_EN (BEA11) = 0 or PCI_EN = 0].  
The C6414T device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414T device, all other  
pins are standalone peripheral functions and are not muxed.  
For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.  
41  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
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