ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
signal groups description (continued)
McBSP1
Transmit
McBSP0
†
CLKX0
FSX0
DX0
CLKX1/URADDR4
†
†
Transmit
FSX1/UXADDR3
DX1/UXADDR4
†
†
†
CLKR1/URADDR2
FSR1/UXADDR2
DR1/UXADDR1
CLKR0
FSR0
Receive
Clock
Receive
Clock
DR0
†
CLKS0
CLKS1/URADDR3
McBSP2
Transmit
†
CLKX2/XSP_CLK
FSX2
†
DX2/XSP_DO
CLKR2
FSR2
Receive
Clock
†
DR2/XSP_DI
McBSPs
(Multichannel Buffered
Serial Ports)
‡
CLKS2/GP8
†
‡
For the C6415T and C6416T devices, these McBSP2 and McBSP1 pins are muxed with the PCI and UTOPIA peripherals, respectively.
By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these muxed pins, see the Device
Configurations section of this data sheet.
For the C6414T device, these McBSP2 and McBSP1 peripheral pins are not muxed; the C6414T device does not support PCI and
UTOPIA peripherals.
The McBSP2 clock source pin (CLKS2, default) is muxed with the GP8 pin. To use this muxed pin as the GP8 signal, the appropriate
GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations
section of this data sheet.
Figure 4. Peripheral Signals (Continued)
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
