ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
signal groups description
RESET
NMI
CLKIN
†
‡
‡
‡
‡
CLKOUT4/GP1
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
Reset and
Interrupts
†
CLKOUT6/GP2
Clock/PLL
CLKMODE1
CLKMODE0
PLLV
RSV
RSV
RSV
RSV
RSV
RSV
TMS
TDO
TDI
TCK
Reserved
•
•
•
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
IEEE Standard
1149.1
(JTAG)
Emulation
RSV
RSV
RSV
PCI_EN
MCBSP2_EN
Peripheral
Control/Status
Control/Status
‡
‡
‡
‡
§
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP3
GP15/PRST
§
§
GP14/PCLK
GP13/PINTA
§
GP12/PGNT
GPIO
§
GP11/PREQ
†
§
CLKOUT6/GP2
CLKOUT4/GP1
GP0
GP10/PCBE3
†
§
GP9/PIDSEL
†
CLKS2/GP8
General-Purpose Input/Output (GPIO) Port
†
These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2
clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be
properly enabled and configured. For more details, see the Device Configurations section of this data sheet.
‡
§
These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
For the C6415T and C6416T devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up
to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device
Configurations section of this data sheet. For the C6414T device, the GPIO peripheral pins are not muxed; the C6414T device does
not support the PCI peripheral.
Figure 3. CPU and Peripheral Signals
32
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