ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
signal groups description (continued)
†
HPI
(Host-Port Interface)
32
Data
HD[31:0]/AD[31:0]
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Register Select
Control
Half-Word
Select
HHWIL/PTRDY
(HPI16 ONLY)
HINT/PFRAME
32
HD[31:0]/AD[31:0]
Data/Address
Clock
GP14/PCLK
GP9/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
GP13/PINTA
HAS/PPAR
GP15/PRST
GP10/PCBE3
HR/W/PCBE2
HDS2/PCBE1
Command
Byte Enable
Control
§
PCBE0
HRDY/PIRDY
HCNTL0/PSTOP
HHWIL/PTRDY
GP12/PGNT
GP11/PREQ
Arbitration
HDS1/PSERR
HCS/PPERR
Error
DX2/XSP_DO
§
Serial
XSP_CS
EEPROM
CLKX2/XSP_CLK
DR2/XSP_DI
‡
PCI Interface
(C6415T and C6416T Only
†
‡
For the C6415T and C6416T devices, these HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For
more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, these HPI pins are
not muxed; the C6414T device does not support the PCI peripheral.
For the C6415T and C6416T devices, these PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI, McBSP2, or GPIO
peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these muxed pins,
see the Device Configurations section of this data sheet. For the C6414T device, the HPI, McBSP2, and GPIO peripheral pins are not
muxed; the C6414T device does not support the PCI peripheral.
§
For the C6414T device, these pins are “Reserved (leave unconnected, do not connect to power or ground).”
Figure 4. Peripheral Signals (Continued)
34
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TI [ TEXAS INSTRUMENTS ]
