ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
−600, −720
−850, −1G
NO.
UNIT
MIN
4
MAX
1
2
3
4
t
t
t
t
Setup time, URDATA valid before URCLK high
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
ns
ns
ns
ns
su(URDV-URCH)
h(URCH-URDV)
su(URAV-URCH)
h(URCH-URAV)
1
4
1
9
t
t
t
t
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
4
1
4
1
ns
ns
ns
ns
su(URENBL-URCH)
h(URCH-URENBL)
su(URSH-URCH)
h(URCH-URSH)
10
11
12
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
−600, −720
−850, −1G
NO.
PARAMETER
UNIT
MIN
MAX
5
6
7
8
t
t
t
t
Delay time, URCLK high to URCLAV driven active value
Delay time, URCLK high to URCLAV driven inactive low
Delay time, URCLK high to URCLAV going Hi-Z
3
12
ns
ns
ns
ns
d(URCH-URCLAV)
3
9
3
12
d(URCH-URCLAVL)
d(URCH-URCLAVHZ)
w(URCLAVL-URCLAVHZ)
18.5
Pulse duration (low), URCLAV low to URCLAV Hi-Z
URCLK
2
1
URDATA[7:0]
URADDR[4:0]
P48
0x1F
N
H1
H2
H3
4
5
3
N
N+1
0x1F
N+2
8
0x1F
7
6
URCLAV
URENB
URSOC
N+1
N+2
10
9
11
12
†
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
†
Figure 60. UTOPIA Slave Receive Timing
130
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