ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 63)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
1
3
4
t
t
t
Cycle time, TCK
35
10
9
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 63)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
2
t
Delay time, TCK low to TDO valid
0
18
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 63. JTAG Test-Port Timing
133
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