ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
†‡
timing requirements for GPIO inputs (see Figure 62)
−600
−720
−850
−1G
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, GPIx high
Pulse duration, GPIx low
8P
8P
ns
ns
w(GPIH)
w(GPIL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
†
switching characteristics over recommended operating conditions for GPIO outputs
(see Figure 62)
−600
−720
−850
−1G
NO.
PARAMETER
UNIT
MIN
MAX
§
§
3
4
t
t
Pulse duration, GPOx high
Pulse duration, GPOx low
24P − 8
24P − 8
ns
ns
w(GPOH)
w(GPOL)
†
§
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO
is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 62. GPIO Port Timing
132
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