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TMS320C6416TZLZ7 参数 Datasheet PDF下载

TMS320C6416TZLZ7图片预览
型号: TMS320C6416TZLZ7
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [FIXED-POINT DIGITAL SIGNAL PROCESSORS]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器时钟
文件页数/大小: 140 页 / 2016 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢈꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢋꢀꢊ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢀ  
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢀ ꢐꢍ ꢕ ꢍ ꢀꢖꢗ ꢂ ꢍ ꢕꢔ ꢖꢗ ꢒ ꢘꢓ ꢆꢏ ꢂꢂꢓ ꢘꢂ  
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005  
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)  
−600  
−720  
−850  
NO.  
UNIT  
−1G  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 − 12P  
5 + 24P  
ns  
ns  
su(DRV-CKXH)  
h(CKXH-DRV)  
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.  
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.  
switching characteristics over recommended operating conditions for McBSP as SPI Master or  
†‡  
Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)  
−600  
−720  
−850  
NO.  
PARAMETER  
UNIT  
−1G  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
1
2
3
t
t
t
Hold time, FSX low after CLKX high  
H − 2 H + 3  
T − 2 T + 1  
ns  
ns  
ns  
h(CKXH-FXL)  
d(FXL-CKXL)  
d(CKXH-DXV)  
#
Delay time, FSX low to CLKX low  
Delay time, CLKX high to DX valid  
−2  
4
12P + 2.8 20P + 17  
12P + 3 20P + 17  
Disable time, DX high impedance following last data bit  
from CLKX high  
6
t
−2  
4
ns  
ns  
dis(CKXH-DXHZ)  
7
t
Delay time, FSX low to DX valid  
L − 2 L + 4  
8P + 2 16P + 17  
d(FXL-DXV)  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.  
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP  
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock  
(CLKX).  
126  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
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