ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ
SPRS226H − NOVEMBER 2003 − REVISED AUGUST 2005
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED)
timing requirements for UTOPIA Slave transmit (see Figure 59)
−600, −720
−850, −1G
NO.
UNIT
MIN
4
MAX
2
3
8
9
t
t
t
t
Setup time, UXADDR valid before UXCLK high
Hold time, UXADDR valid after UXCLK high
Setup time, UXENB low before UXCLK high
Hold time, UXENB low after UXCLK high
ns
ns
ns
ns
su(UXAV-UXCH)
1
h(UXCH-UXAV)
4
su(UXENBL-UXCH)
h(UXCH-UXENBL)
1
switching characteristics over recommended operating conditions for UTOPIA Slave transmit
(see Figure 59)
−600, −720
−850, −1G
NO.
PARAMETER
UNIT
MIN
3
MAX
12
1
4
t
t
t
t
t
t
Delay time, UXCLK high to UXDATA valid
ns
ns
ns
ns
ns
ns
d(UXCH-UXDV)
Delay time, UXCLK high to UXCLAV driven active value
Delay time, UXCLK high to UXCLAV driven inactive low
Delay time, UXCLK high to UXCLAV going Hi-Z
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
Delay time, UXCLK high to UXSOC valid
3
12
d(UXCH-UXCLAV)
d(UXCH-UXCLAVL)
d(UXCH-UXCLAVHZ)
w(UXCLAVL-UXCLAVHZ)
d(UXCH-UXSV)
5
3
12
6
9
18.5
7
3
10
3
12
UXCLK
1
3
P45
P46
N
P47
0x1F
N
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
†
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and
UXSOC signals).
†
Figure 59. UTOPIA Slave Transmit Timing
129
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