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TMS320F2809 参数 Datasheet PDF下载

TMS320F2809图片预览
型号: TMS320F2809
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 134 页 / 1127 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F2809, TMS320F2808, TMS320F2806  
TMS320F2802, TMS320F2801, UCD9501  
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs  
www.ti.com  
SPRS230HOCTOBER 2003REVISED JUNE 2006  
Table 3-15. PLLCR Register Bit Definitions  
SYSCLKOUT  
(CLKIN)(2)  
PLLCR[DIV](1)  
0000 (PLL bypass)  
0001  
OSCCLK/n  
(OSCCLK*1)/n  
(OSCCLK*2)/n  
(OSCCLK*3)/n  
(OSCCLK*4)/n  
(OSCCLK*5)/n  
(OSCCLK*6)/n  
(OSCCLK*7)/n  
(OSCCLK*8)/n  
(OSCCLK*9)/n  
(OSCCLK*10)/n  
reserved  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011-1111  
(1) This register is EALLOW protected.  
(2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output  
clock from the CPU. The frequency of SYSCLKOUT is the same as  
CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.  
NOTE  
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed  
to the core. This bit must be 0 before writing to the PLLCR and must only be set after  
PLLSTS[PLLLOCKS] = 1.  
The PLL-based clock module provides two modes of operation:  
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base  
to the device.  
External clock source operation - This mode allows the internal oscillator to be bypassed. The device  
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.  
Table 3-16. Possible PLL Configuration Modes  
SYSCLKOUT  
(CLKIN)  
PLL MODE  
REMARKS  
PLLSTS[CLKINDIV]  
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block  
is disabled in this mode. This can be useful to reduce system noise and for low  
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)  
before entering this mode. The CPU clock (CLKIN) is derived directly from the  
input clock on either X1/X2, X1 or XCLKIN.  
0
OSCCLK/2  
PLL Off  
1
OSCCLK  
PLL Bypass is the default PLL configuration upon power-up or after an external  
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or  
while the PLL locks to a new frequency after the PLLCR register has been  
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.  
0
1
OSCCLK/2  
OSCCLK  
PLL Bypass  
PLL Enable  
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the  
PLLCR the device will switch to PLL Bypass mode until the PLL locks.  
0
OSCCLK*n/2  
3.6.1.3 Loss of Input Clock  
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still  
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical  
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have  
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to  
the CPU if the input clock is removed or absent.  
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog  
48  
Functional Overview