TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230H–OCTOBER 2003–REVISED JUNE 2006
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-14.
Table 3-14. PLL, Clocking, Watchdog, and Low-Power Mode Registers(1)
NAME
XCLK
ADDRESS
0x7010
SIZE (x16)
DESCRIPTION
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLL Status Register
1
1
8
1
1
1
1
1
1
1
1
1
1
1
3
1
6
PLLSTS
reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
reserved
PLLCR
0x7011
0x7012 - 0x7019
0x701A
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
Peripheral Clock Control Register 0
0x701B
0x701C
0x701D
Peripheral Clock Control Register 1
0x701E
Low Power Mode Control Register 0
0x701F - 0x7020
0x7021
PLL Control Register
SCSR
0x7022
System Control and Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
reserved
WDCR
0x7023
0x7024
0x7025
Watchdog Reset Key Register
Watchdog Control Register
0x7026 - 0x7028
0x7029
reserved
0x702A - 0x702F
(1) All of the registers in this table are EALLOW protected.
3.6.1 OSC and PLL Block
Figure 3-10 shows the OSC and PLL block on the 280x.
OSCCLK
OSCCLK
XCLKIN
(3.3-V clock input)
0
n
xor
OSCCLK or
VCOCLK
CLKIN
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
VCOCLK
PLL
/2
n ≠ 0
PLLSTS[CLKINDIV]
X1
On chip
oscillator
4-bit PLL Select (PLLCR)
X2
Figure 3-10. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO
.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD
.
The three possible input-clock configurations are shown in Figure 3-11 through Figure 3-13
46
Functional Overview
TI [ TEXAS INSTRUMENTS ]
