TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x System Control and Interrupts Reference
Guide (literature number SPRU712).
3.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-9 shows the various clock and reset domains in the 280x devices that will be
discussed.
Reset
SYSCLKOUT
XRS
Watchdog
Block
(A)
Peripheral Reset
X1
X2
(A)
CLKIN
28x
CPU
PLL
OSC
Power
Modes
Control
XCLKIN
CPU
Timers
Peripheral
Registers
Clock Enables
System
Control
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
Peripheral
Registers
I/O
I/O
I/O
eCAN-A/B
I C-A
Peripheral
Registers
2
GPIO
MUX
GPIOs
Low-Speed Prescaler
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC inputs
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-9. Clock and Reset Domains
Functional Overview
45
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