TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
3.5 Interrupts
Figure 3-7 shows how the various interrupt sources are multiplexed within the 280x devices.
Peripherals
2
(SPI, SCI, I C, eCAN, ePWM, eCAP, eQEP, ADC)
WDINT
Watchdog
Low Power Modes
WAKEINT
XINT1
LPMINT
XINT1
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
CPU
GPIOXINT2SEL(4:0)
TINT0
CPU TIMER 0
TINT2
TINT1
CPU TIMER 2 (for TI/RTOS)
CPU TIMER 1 (for TI)
INT14
INT13
int13_select
nmi_select
GPIO0.int
XNMI_XINT13
GPIO
MUX
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
Figure 3-7. External and PIE Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as
shown in Table 3-11.
42
Functional Overview
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