TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-8. Multiplexing of Interrupts Using the PIE Block
Table 3-11. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
INT2
INT3
INT4
INT5
XINT2
XINT1
reserved
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
reserved
reserved
reserved
reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
reserved
reserved
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
SPITXINTC
(SPI-C)
SPIRXINTC
(SPI-C)
SPITXINTB
(SPI-B)
SPIRXINTB
(SPI-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT6
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
Functional Overview
43
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