TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
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SPRS230H–OCTOBER 2003–REVISED JUNE 2006
Table 3-7. Peripheral Frame 0 Registers(1)(2)
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE(3)
EALLOW protected
Device Emulation Registers
0x0880 - 0x09FF
384
EALLOW protected
CSM Protected
FLASH Registers(4)
0x0A80 - 0x0ADF
96
Code Security Module Registers
ADC Result Registers (dual-mapped)
CPU-TIMER0/1/2 Registers
PIE Registers
0x0AE0 - 0x0AEF
0x0B00 - 0x0B0F
0x0C00 - 0x0C3F
0x0CE0 - 0x0CFF
0x0D00 - 0x0DFF
16
16
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
64
32
PIE Vector Table
256
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-8. Peripheral Frame 1 Registers(1)(2)
NAME
ADDRESS RANGE
0x6000 - 0x60FF
0x6100 - 0x61FF
0x6200 - 0x62FF
SIZE (x16)
256
ACCESS TYPE
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
eCANA Registers
eCANA Mailbox RAM
eCANB Registers
256
Not EALLOW-protected
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
256
eCANB Mailbox RAM
ePWM1 Registers
0x6300 - 0x63FF
0x6800 - 0x683F
0x6840 - 0x687F
0x6880 - 0x68BF
0x68C0 - 0x68FF
0x6900 - 0x693F
0x6940 - 0x697F
0x6A00 - 0x6A1F
0x6A20 - 0x6A3F
0x6A40 - 0x6A5F
0x6A60 - 0x6A7F
0x6B00 - 0x6B3F
0x6B40 - 0x6B7F
0x6F80 - 0x6FBF
0x6FC0 - 0x6FDF
0x6FE0 - 0x6FFF
256
64
64
64
64
64
64
32
32
32
32
64
64
128
32
32
Not EALLOW-protected
ePWM2 Registers
Some ePWM registers are EALLOW
protected.
See Table 4-2
ePWM3 Registers
ePWM4 Registers
ePWM5 Registers
ePWM6 Registers
eCAP1 Registers
eCAP2 Registers
eCAP3 Registers
Not EALLOW protected
eCAP4 Registers
eQEP1 Registers
eQEP2 Registers
GPIO Control Registers
GPIO Data Registers
GPIO Interrupt and LPM Select Registers
EALLOW protected
Not EALLOW protected
EALLOW protected
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.
40
Functional Overview
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