TMP112
SBOS473B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
TWO-WIRE TIMING DIAGRAMS
t(LOW)
tF
tR
t(HDSTA)
SCL
SDA
t(HDSTA)
t(HIGH) t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(BUF)
P
S
S
P
Figure 15. Two-Wire Timing Diagram
1
9
1
9
SCL
¼
¼
A1(1) A0(1)
SDA
1
0
0
1
0
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
ACK By
TMP112
TMP112
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4 D3
D2 D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
(Continued)
ACK By
ACK By
Stop By
Master
TMP112
TMP112
Frame 3 Data Byte 1
Frame 4 Data Byte 2
NOTE: (1) The values of A0 and A1 are determined by the ADD0 pin.
Figure 16. Two-Wire Timing Diagram for Write Word Format
14
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