TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
dual-in-line memory module and components
The dual-in-line memory module and components include:
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2SN64EPU
S0
R
R
C
C
CK: U0, U4
CK: U1, U5
CS
CS
CK0
R
R
C
C
U0
U4
CK: U2, U6
CK: U3, U7
CK1
CK2
DQMB0
DQ[0:7]
DQM
DQMB4
DQM
R
R
8
8
DQ[0:7]
DQ[32:39]
DQ[0:7]
R
R
C
C
C
C
CS
CS
CK3
U1
U5
DQMB1
DQM
DQMB5
DQM
R
R
8
8
DQ[8:15]
DQ[0:7]
DQ[40:47]
DQ[0:7]
R = 10 Ω
R
= 10 Ω
C
C = 10 pF
S2
V
DD
U[0:7]
Two 0.1 µF
(minimum) per
SDRAM
CS
CS
V
SS
U[0:7]
U2
U6
DQMB2
DQM
DQMB6
DQM
R
R
8
8
DQ[16:23]
DQ[0:7]
DQ[48:55]
DQ[0:7]
SPD EEPROM
CS
CS
SCL
SDA
A0
A1
A2
U3
U7
=
SA0 SA1 SA2
DQMB3
DQM
DQMB7
DQM
R
R
8
8
DQ[24:31]
DQ[0:7]
DQ[56:63]
DQ[0:7]
RAS
CAS
WE
CKE0
A[0:11]
RAS: SDRAM U[0:7]
CAS: SDRAM U[0:7]
WE: SDRAM U[0:7]
CKE: SDRAM U[0:7]
A[0:11]: SDRAM U[0:7]
LEGEND: CS
Chip select
SPD = Serial Presence Detect
4
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