TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM2SN64EPU TM4SN64EPU
(SIDE VIEW) (SIDE VIEW)
PIN NOMENCLATURE
A[0:10]
A[0:8]
Row Address Inputs
Column Address Inputs
Bank-Select Zero
Column-Address Strobe
Clock Enable
A11/BA0
CAS
CKE[0:1]
CK[0:3]
DQ[0:63]
DQMB[0:7]
1
System Clock
Data-In/Data-Out
Data-In/Data-Out
Mask Enable
10
11
NC
RAS
S[0:3]
SA[0:2]
No Connect
Row-Address Strobe
Chip-Select
Serial Presence-Detect (SPD)
Device Address Input
SPD Clock
SPD Address/Data
3.3-V Supply
SCL
SDA
V
DD
V
SS
Ground
WE
Write Enable
40
41
84
2
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