TLK10002
SLLSE75 –MAY 2011
www.ti.com
HS_ SERDES_CONTROL_3 — Address: 0x04 Default: 0xB820
BIT(s)
NAME
DESCRIPTION
ACCESS
4.15
HS_ENTRACK
HSRX ADC Track mode
RW
0 = Normal operation
1 = Forces ADC into track mode (Default 1’b1)
4.14:12
HS_EQPRE[2:0]
SERDES Rx precursor equalizer selection
RW
000 = 1/9 cursor amplitude
001 = 3/9 cursor amplitude
010 = 5/9 cursor amplitude
011 = 7/9 cursor amplitude (Default 3’b011)
100 = 9/9 cursor amplitude
101 = 11/9 cursor amplitude
110 = 13/9 cursor amplitude
111 = Disable
4.11:10
4.9:8
HS_CDRFMULT[1:0] Clock data recovery algorithm frequency multiplication selection
RW
RW
00 = First order. Frequency offset tracking disabled
01 = Second order. 1x mode
10 = Second order. 2x mode (Default 2’b10)
11 = Reserved
HS_CDRTHR[1:0]
Clock data recovery algorithm threshold selection
00 = Four vote threshold (Default 2’b00)
01 = Eight vote threshold
10 = Sixteen vote threshold
11 = Thirty two vote threshold
4.7
4.6
HS_EQLIM
HS_EQHLD
HSRX Equalizer limit control
RW
RW
0 = Normal operation (Default 1’b0)
1 = Limits equalizer DFE tap weights
HSRX Equalizer hold control
0 = Normal operation (Default 1’b0)
1 = Holds equalizer and long tail correction in their current state
4.5
HS_H1CDRMODE
HS_TWCRF[4:0]
0 = CDR locks to h(-1)
RW
RW
1 = CDR locks to h(+1)
4.4:0
Cursor Reduction Factor (Default 5’b00000) Refer to Table 12
36
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