TLK10002
SLLSE75 –MAY 2011
www.ti.com
HS_ SERDES_CONTROL_2 — Address: 0x03 Default: 0xA444
BIT(s)
NAME
DESCRIPTION
ACCESS
RW
3.15:12 HS_SWING[3:0]
Transmitter Output swing control for HS SERDES. (Default 4’b1010) Refer to Table 11
For TI use only (Default 1’b0)
3.11
3.10
RESERVED
HS_ENTX
RW
HS SERDES transmitter enable control. HS SERDES transmitter is automatically disabled
when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.
RW
0 = Disables HS SERDES transmitter
1 = Enables HS SERDES transmitter (Default 1’b1)
3.9:8
3.7:6
HS_RATE_TX [1:0]
HS_AGCCTRL[1:0]
HS SERDES TX rate settings
RW
RW
00 = Full rate (Default 2’b00)
01 = Half rate
10 = Quarter rate
11 = Eighth rate
Adaptive gain control loop
00 = Attenuator will not change after lock has been achieved, even if AGC becomes
unlocked
01 = Attenuator will not change when in lock state, but could change when AGC
becomes unlocked (Default 2’b01)
10 = Force the attenuator off.
11 = Force the attenuator on
Auto zero calibration.
3.5:4
HS_AZCAL[1:0]
RW
00 = Auto zero calibration initiated when receiver is enabled (Default 2’b00)
01 = Auto zero calibration disabled
10 = Forced with automatic update.
11 = Forced without automatic update
3.3
HS_ENUNSD
HS_ENRX
0 = Disable use of unscrambled data in HS Serdes Rx (Recommended setting for Full
RW
RW
RW
Rate) (Default 1’b0)
1 = Enable use of unscrambled data in HS Serdes Rx (Recommended setting for Half,
Quarter and Eighth Rates)
3.2
HS SERDES receiver enable control. HS SERDES receiver is automatically disabled when
PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.
0 = Disables HS SERDES receiver
1 = Enables HS SERDES receiver (Default 1’b1)
3.1:0
HS_RATE_RX [1:0]
HS SERDES RX rate settings
00 = Full rate (Default 2’b00)
01 = Half rate
10 = Quarter rate
11 = Eighth rate
34
Copyright © 2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
