TLK10002
SLLSE75 –MAY 2011
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Protocol FPGA (Channel A Only )
TLK10002 (Channel A Only )
LAS
LS _OK_OUT_A
Lane Alignment Slave
LAM
CH
SYNC
?
10B 8B
?
8B 10B
Lane
Alignment
Master
CH
SYNC
CH
SYNC
?
10B 8B
?
8B 10B
Lane
Align
INA[3:0]P/N
?
10B 8B
?
8B 10B
Low
Speed
Side
Low
Speed
Side
CH
SYNC
?
10B 8B
?
8B 10B
SERDES
Channel A
(4 RX/ 4 TX)
SERDES
Channel A
(4RX / 4 TX)
CH
SYNC
CH
SYNC
CH
SYNC
CH
SYNC
?
8B 10B
?
10B 8B
LAM
Lane
Alignment
Master
?
8B 10B
?
10B 8B
Lane
Align
OUTA[3:0]P/N
?
8B 10B
?
10B 8B
?
8B 10B
?
10B 8B
LAS
Lane Alignment Slave
LS _OK _IN_A
Figure 8. Block Diagram of the Lane Alignment Scheme
12
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TI [ TEXAS INSTRUMENTS ]
