TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. When the following conditions exist, a FIFO character time-out interrupt occurs:
a. Minimum of one character in FIFO
b. The last received serial character is longer than four previous continuous-character times (if two stop
bits are programmed, the second one is included in the time delay).
c. The last CPU read of the FIFO is more than four previous continuous-character times. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.1
2. By using the RCLK input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received when
there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCR0 = 1, IER = 1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time when the
following occurs:
THRE = 1 and there is not a minimum of two bytes at the same time in transmitter FIFO since the last
THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, assuming it is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the received data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
Clearing IER0, IER1, IER2, IER3, or all with FCR0 = 1 puts the ACE into the FIFO polled mode. The receiver
and transmitter are controlled separately. Either one or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
ACE status.
interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INT0 or
INT1) output. All interrupts are disabled by clearing IER0 – IER3. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the interrupt identification register and the
active (high) interrupt output. All other system functions operate in their normal manner, including the setting
of the LSRs and MSRs. The contents of the IER shown in Table 3 are described in the following bulleted list.
Bit 0: When IER0 is set, IER0 enables the received data available interrupt and the time-out interrupts in
the FIFO mode.
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