TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the internal registers are shown in Table 1.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
Line control register
FIFO control register
Modem control register
Divisor latch LSB
MNEMONIC
LCR
STATUS
MNEMONIC
LSR
DATA
MNEMONIC
RBR
Line status register
Modem status register
Receiver buffer register
Transmitter holding register
FCR
MSR
THR
MCR
DLL
Divisor latch MSB
DLM
Interrupt enable register
IER
The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register (bit 7)
to select the register to be written to or read from (see Table 2). Individual bits within the registers are referred to by
the register mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
The transmitter holding register and receiver buffer register are data registers that hold from five to eight bits of data.
If fewer than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first
serial data bit received and transmitted. The ACE data registers are double buffered (TL16C450 mode) or FIFO
buffered (FIFO mode) so that read and write operations can be performed when the ACE is performing the
parallel-to-serial or serial-to-parallel conversion.
†
Table 2. Register Selection
DLAB
A2
L
A1
L
A0
L
MNEMONIC
RBR
THR
IER
REGISTER
Receiver buffer register (read only)
Transmitter holding register (write only)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write only)
Line control register
L
L
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
H
H
L
H
H
H
L
IIR
L
L
FCR
LCR
L
H
L
H
H
H
H
L
MCR
LSR
Modem control register
L
H
L
Line status register
H
H
L
MSR
SCR
DLL
Modem status register
H
L
Scratch pad register
LSB divisor latch
L
L
H
DLM
MSB divisor latch
†
The serial channel is accessed when either CS0 or CS1 is low.
X = irrelevant, L = low level, H = high level
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