TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Line Control Register
LCR LCR LCR LCR LCR LCR LCR LCR
7
6
5
4
3
2
1
0
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
Word Length
Select
0 = 1 Stop Bits
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Stop Bit
Select
0 = Parity Disabled
1 = Parity Enabled
Parity Enable
0 = Odd Parity
1 = Even Parity
Even Parity
Select
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Stick Parity
0 = Break Disabled
1 = Break Enabled
Break Control
Divisor Latch
Access Bit
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 19. Line Control Register Contents
line printer port
The line printer port contains the functionality of the port included in the TL16C452 but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PE) terminal. This enhancement
is the addition of a direction control bit and an interrupt status bit.
register 0 line printer data register
The line printer (LPT) port is either output only or bidirectional depending on the state of the extended mode
terminal and data direction control bits.
Compatibility mode (PEMD = L)
Reads to the LPT data register and returns the last data that was written to the port. Write operations
immediately output data to PD0–PD7.
Extended mode (PEMD = H)
ReadoperationsreturneitherthedatalastwrittentotheLPTdataregisterwhenthedirectionbitisclearedor
return the data that is present on PD0 – PD7 when the direction is set to read. Write operations to the LPT
dataregisterlatchdataintotheoutputregister;however, theyonlydrivetheLPTportwhenthedirectionbitis
cleared.
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