TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
accessible registers
Using the CPU, the system programmer has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER BIT NUMBER
REGISTER
MNEMONIC
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RBR
(read only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
0
THR
(write only)
Data
Bit 7
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
†
†
0
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
1
DLM
IER
Bit 15
0
Bit 14
0
Bit 13
0
Bit 12
0
Bit 11
Bit 10
1
(EDSSI) Enable
modem status
interrupt
(ERLSI)
Enable
receiver line
status
(ETBEI)
Enable
transmitter
holding
(ERBFI)
Enable
received
data
interrupt
register
empty
available
interrupt
interrupt
2
2
FCR
(write only)
Receiver
trigger (MSB) trigger (LSB)
Receiver
Reserved
0
Reserved
0
DMA
mode select
Transmitter
FIFO reset
Receiver
FIFO reset
FIFO
enable
IIR
(read only)
FIFOs FIFOs
Interrupt ID
‡
bit 3
Interrupt ID
bit 2
Interrupt ID
bit 1
0 if
interrupt
pending
‡
‡
enabled
enabled
3
4
LCR
(DLAB)
Divisor latch
access bit
Set
break
Stick
parity
(EPS)
Even parity
select
(PEN)
Parity enable
(STB)
Number of
stop bits
(WLSB1)
Word length
select bit 1
(WLSB0)
Word length
select bit 0
MCR
0
0
0
Loop
OUT2 Enable
external
interrupt
OUT1
(an unused
internal
(RTS)
Request
to send
(DTR)
Data
terminal
ready
(INT0 or INT1)
signal)
5
6
LSR
Error in
receiver
FIFO
(TEMT)
Transmitter
empty
(THRE)
Transmitter
holding
register
empty
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
Parity
error
(OE)
Overrun
error
(DR)
Data
ready
‡
MSR
SCR
(DCD)
Data carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear
to send
(∆DCD)
Delta data
carrier detect
(TERI)
Trailing edge
ring indicator
(∆DSR)
Delta data
set ready
(∆CTS)
Delta clear
clear to send
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
†
‡
DLAB = 1
These bits are always 0 when FIFOs are disabled.
19
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