TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
line printer port (continued)
Table 6 summarizes the configuration of the PD port based on the combinations of the logic level on the
PEMD terminal and the value of the direction control bit (DIR).
Table 6. Extended Mode and Direction Control Bit Combinations
PEMD
DIR
X
PD0–PD7 FUNCTION
PC/AT mode – output
PS/2 mode – output
PS/2 mode – input
L
H
H
0
1
register 1 read line printer status register
The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT
connector terminals. Table 7 (in the default column) shows the values of each bit after reset in the case of the
printer being disconnected from the port.
Table 7. LPS Register Bit Description
BIT
0
DESCRIPTION
Reserved
Reserved
PRINT
ERR
DEFAULT
1
1
1
†
†
†
†
†
1
2
3
4
SLCT
5
PE
6
ACK
7
BSY
†
Outputs are dependent upon device inputs.
Bits 0 and 1: LPS0 and LPS1 are reserved and always set.
Bit 2: LPS2 is the printer interrupt (PRINT, active low) status bit. When cleared, LPS2 indicates that the
printer has acknowledged the previous transfer with an ACK handshake (if bit 4 of the control register is set).
The bit is cleared on the active-to-inactive transition of the ACKsignal. This bit is set after a read of the status
port.
Bit 3: ERR is the error status bit and corresponds to ERR input.
Bit 4: SLCT is the select status bit and corresponds to SLCT input.
Bit 5: PE is the paper empty status bit and corresponds to PE input.
Bit 6: ACK is the acknowledge status bit corresponds to ACK input.
Bit 7: BSY is the busy status bit and corresponds to BUSY input (active high).
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