TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Start
Data Bits 5–8
Parity
Stop
SIN
Sample
CLK
(FIFO at or above
trigger level)
Trigger
Interrupt
(FCR6, 7=0, 0)
50%
50%
(FIFO below
trigger level)
t
t
d9
pd7
IOR
(RD RBR)
Active
50%
50%
50%
LSI
Interrupt
t
pd7
Active
IOR
50%
(RD LSR)
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
SIN
Stop
Sample
CLK
t
d9
(see Note A)
Time Out or
Trigger Level
Interrupt
(FIFO at or above
trigger level)
50%
50%
(FIFO below
trigger level)
t
pd7
LSI
Interrupt
50%
50%
Top Byte of FIFO
t
pd7
t
d9
IOR
(RD LSR)
50%
Active
IOR
(RD RBR)
50%
50%
Active
Active
Previous Byte
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
14
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